The present invention relates to the manufacturing of semiconductor devices, and more particularly, to laser anneal processes that prevent polysilicon depletion.
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS semiconductor device generally includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS transistor is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
MOS devices typically fall in one of two groups depending the type of dopants used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
A type of device, commonly referred to as a MOS field-effect-transistor (MOSFET), includes a channel region formed in the semiconductor substrate beneath the gate area or electrode and between the source and drain regions. The channel is typically lightly doped with a dopant having a conductivity type opposite to that of the source/drain regions. The gate electrode is generally separated from the substrate by an insulating layer, typically an oxide layer such as SiO2. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, drain or channel regions. In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner an electric field is used to control the current flow through the channel region.
The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant performance increases, for example, from decreasing performance degrading resistances and parasitic capacitances. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOSFET structures.
As the dimensions of the MOSFET shrinks, the reduction in effective gate length requires a proportional scaling in the vertical junction depth of the source/drain regions. The reduction in the junction depth of the source/drain regions is to reduce short channel effects.
As the distance between the source region and the drain region of the MOSFET (i.e., the physical channel length) decreases, in the effort to increase circuit speed and complexity, the junction depth of source/drain regions must also be reduced to prevent unwanted source/drain-to-substrate junction capacitance. However, obtaining these smaller junction depths test the capabilities of current processing techniques, such as ion implantation with activation annealing using rapid thermal annealing. Rapid thermal annealing typically involves heating the silicon wafer, after implanting, under high-intensity heat lamps. Implanting or doping creates an amorphitizes the silicon substrate, and the activation annealing is used to recrystallize the amorphitized silicon region.
As a result of the limitations of rapid thermal annealing, laser thermal annealing is being implemented, particularly for ultra-shallow junction depths. Laser thermal annealing may be performed after ion implantation of a dopant and involves heating the doped area with a laser. The laser radiation rapidly heats the exposed silicon such that the silicon begins to melt. The diffusivity of dopants into molten silicon is about 8 orders of magnitude higher than in solid silicon. Thus, the dopants distribute almost uniformly in the molten silicon and the diffusion stop almost exactly at the liquid/solid interface. The heating of the silicon is followed by a rapid quench to solidify the silicon, and this process allows for non-equilibrium dopant activation in which the concentration of dopants within the silicon is above the solid solubility limit of silicon. Advantageously, this process allows for ultra-shallow source/drain regions that have an electrical resistance about one-tenth the resistance obtainable by conventional rapid thermal annealing.
The abbreviation for MOS (metal-oxide-semiconductor) can be somewhat of a misnomer, as the gate, in many applications, is formed of a polysilicon material deposited over a gate oxide with the polysilicon material being doped to render it conductive. One problem that is encountered with the formation of ultra-shallow source/drain regions results from the polysilicon gate thickness not being scaled down at the same rate as the source/drain regions. Consequently, this scaling discrepancy worsens polysilicon depletion, which is also known as poly depletion. As commonly understood by those skilled in the art, poly depletion worsens when an anneal subsequent to the doping of a polysilicon gate is insufficient to drive the implanted dopants down the entire depth of the polysilicon gate. Consequently, a portion of the polysilicon gate nearest the gate oxide is depleted of dopants and behaves as an insulating region. As a result, the resulting transistor behaves as though the gate oxide is substantially thicker, thereby resulting in a substantial degradation of device performance or even rendering the device inoperable.
Increasing the implant energy or subsequent anneal time to remedy the poly depletion creates another problem, as these process modifications can cause the shallow source/drain regions to increase in depth. Consequently, a performance trade-off exists between reduced poly depletion and ultra-shallow source/drain junctions. Accordingly, a need exists for an improved process that has the benefits of laser thermal annealing while minimizing poly depletion.
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device that reduces poly depletion. The method comprises forming a gate electrode oxide over a substrate; depositing a first layer of polysilicon over the gate oxide; implanting dopants in the first layer; depositing a second layer of polysilicon over the first layer, etching both layers to form a gate electrode; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate; and laser thermal annealing to activate the source/drain regions and to melt the first layer.
The doping of the first layer of polysilicon amorphitizes the first layer, and subsequent laser thermal annealing melts the amorphitized first layer. Also, the doping of the first layer provides a high concentration of dopants at the interface of the gate oxide and the gate electrode after the first layer has been melted. This high concentration of dopants improves the conductivity of the polysilicon layer and reduces poly depletion effects.
In a further aspect of the present invention, the first layer can have a depth of about 200 to 500 angstroms, and the second layer can have a depth of about 300 to 4500 angstroms. Also, the source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. Furthermore, the laser thermal annealing can also melt amorphitized portions of the second layer.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.